Nexora Systems · Digital Semiconductor

Hardware depth.
Software reach.

A systems perspective spanning semiconductor physical design, programmable hardware, knowledge software and the interfaces that connect technical capability to real-world operation.

Physical designFPGA systemsChiplets & 2.5DAI accelerators
DigitalSEMICONDUCTORSystems perspective
01HardwareSilicon · FPGA · Packaging
02SoftwareKnowledge · Control · Operation

Engineering foundation

System thinking shaped by semiconductor physical design.

Nexora’s connected-systems perspective is informed by experience navigating physical-design constraints, performance-power-area trade-offs, cross-functional dependencies and the path towards GDSII sign-off.

That background strengthens how we think about interfaces, bottlenecks, hand-offs, validation and the reliability of an end-to-end operating system.

Watch: From PPA bottlenecks to GDSII sign-off ↗

Two disciplines, deliberately separated

Hardware and software solve different parts of the system.

Separating them creates clarity. Connecting them creates operational value.

01 / Hardware

Architecture constrained by physics.

Work shaped by latency, throughput, area, power, packaging, memory movement and implementation feasibility.

  • FPGA and accelerator architecture
  • ASIC, GPU and FPGA workload selection
  • Chiplet and 2.5D integration
  • Physical design, PPA and GDSII
  • Hardware control and data movement
02 / Software

Intelligence organised for action.

Software connects technical capability with knowledge, users, workflows and the operating decisions around it.

  • RAG and MCP knowledge systems
  • AI assistants and application interfaces
  • CRM and operational integration
  • Business workflows and automation
  • Dashboards, monitoring and reporting

Technical writing on Medium

Semiconductor architecture, markets and implementation.

Selected writing translating technical systems into strategic and operational insight.

Architecture · Enterprise AIThe Architecture That Will Shape the Future of Enterprise

From GPUs to cloud AI—and the architecture forming between them.

Read on Medium ↗ Semiconductor strategyMicrochip Technology: A SKU Giant in an AI World of High-Volume Titans

A CapitalCompass perspective on portfolio breadth and the economics of scale.

Read on Medium ↗ Advanced packagingTSMC’s CoWoS Monopoly

The silent superpower behind the AI era—and why packaging matters as much as the chip.

Read on Medium ↗ Hardware architectureFPGA vs ASIC vs GPU: Choosing the Right Hardware for the Right Job

Matching flexibility, latency, power and scale to the workload.

Read on Medium ↗ FPGA implementationOffloading Smart: How I Used NIOS II to Improve FPGA Control & I/O Flow

Separating control from acceleration to create a cleaner programmable-hardware system.

Read on Medium ↗

Research & publication

Published work in chiplets and AI accelerators.

Co-authored three IEEE conference papers on chiplet-based architectures and AI accelerators, translating research into manufacturing innovation at A*STAR.

IEEE EPTC2021

Chiplet-based Architecture Design for Multi-Core Neuromorphic Processor

A reusable multi-chip architecture addressing throughput, energy efficiency and manufacturing cost through scalable 2.5D integration.

View IEEE publication ↗
IEEE EPTC2020

An Automatic Chip-Package Co-Design Flow for Multi-Core Neuromorphic Computing SiPs

An automated chiplet co-design flow spanning RTL generation, inter-chiplet routing, parasitic extraction and interposer implementation.

View IEEE publication ↗
IEEE IECON2020

Area and Energy Efficient 2D Max-Pooling for Convolutional Neural Network Hardware Accelerator

A hardware-efficient CNN max-pooling design focused on throughput, area and power for accelerator implementation.

View IEEE publication ↗
Innovate Malaysia Design Competition2014 · FPGA Track

Authored project

High Performance DNA Sequencer for Early Stage Cancer Detection

Hardware or software—start with the system

Connect technical depth to an operating outcome.

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